HD-BU

“HD-BU”, abbreviated from High Density Build Up, is an ultra thin, fine pitch package with exposed die attach pad feature for excellent electrical & thermal performance. “HD-BU” is a lead-free, multi-row, array package solution and provides a high flexibility for design for most of chip scale applications.

HDL

The High Density Leadframe (HDL) is the latest innovation in the QFN (Quad Flat No-Lead ) packaging evolution that delivers the greatest number of leads per body size while delivering the highest performance at a lower cost. The HDL package and processes were invented and developed by Mr. Li Tung Lok (TL Li) of QPL Limited and uses high density leadframe routing to allow contacts to cover the total bottom area of the package.The HDL’s unique two-step LF etching process allows the package to be designed around the die and application and results in the shortest wire bond lengths of any wire bonded technology. With outstanding electrical, thermal, and MSL level 1 performance, the HDL package is ideal for single die, MCM and SIP applications using either Flip Chip and/or Wire Bonding connections. The IC Packaging Technology of the future is here today with HDL solutions.

PDIP / SPDIP

The Plactic Dual In-line Package/Shrink Plastic Dual In-line Package has a rectangular plastic body with two rows of leads that are bent up from the package body at a slight angle. Its most common use is through-hole insertion mounting in applications such as logic, processor and memory devices. QPL also delivers IDF(Interdigitated Frame) versions that enable more lead frames to be oriented along a strip, resulting in increased throughput in assembly.

The Plastic Leaded Clip Carrier has leads on all four sides with J-shaped beds and is available with a variety of pad designs, such as dual-pad. Designs with fused leads promote better thermal performance, while those with a closed dambar reduce mold flash and improve the solder plating coverage.

QFN

The Quad Flat Non-Lead package type delivers the small footprint and low pin count needed for today's portable devices and high-speed application demanding high electrical performance in a constrained area. QFNs are miniaturized, low pin-count, perimeter-array package that use a metallic lead frame for the die assembly and board interconnection. This design allows the use of standard die-attach, wire-bond and encapsulation technologies and equipment. QFN is a lead frame-base CSP (Chip Scale Package) type of package with a "leadless" element that enables superior thermal performance and the ability to view and contact leads after assembly.

QFP / TQFP

The Quad Flat Pack/Thin Quad Flat Pack is a plastic package with a square or rectangular body with leads on all four sides in a gull-wing configuration. Designs with "dimples" (half-etched holes) on the back side of the pad provide the mechanical adhesion to prevent delamination. Different pad designs exist to further enhance package reliability, while designs with a dual-pad lead frame are available to minimize cost.

The Small Outline Intergrated Circuit is available in a number of variations, including SOP(Small Outliine Package), SSOP(Shrink Small Outline Package), SOJ(Small Outline J-Leaded),
TSOP(Thin Small Outline Package), and TSSOP(Thin Shrink Small Outline Package). The SOIC package is desirable for its small footprint on the circuit board. SO lead frames are available in single-pad, dual-pad and matrix designs.

Thermal Enhanced Products

TBGA Stiffeners, heatsinks and lids are used in TBGA packages, flip chip, EBGA packages and leadframe based packages for thermal
management, die protection and mechanical support. Depending on the type of IC is mounted and draws heat from the reverse side of the die for
dissipation directly to ambient or via an attached heatsink in heat slugs embedded in the package assembly and serve as both heat dissipation route
and as a stiffener.

TSOP / LOC

The Lead On Chip features lead fingers that are attached directly to the surface of the chip using a double-sided adhesive tape. Since there is no die pad on the LOC lead frame, the package allows for higher density, enabling it to accommodate a larger IC chip and providing better reliability performance than traditional packages. These characteristics make LOC packaging a good choice meeting the increasing capacity and density requirements of DRAM (Dynamic Random Access Memory) designs.